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LTC2413 24-Bit No Latency TM ADC, with Simultaneous 50Hz/60Hz Rejection
FEATURES
s s
DESCRIPTIO
s s s s s
s
s s s
Simultaneous 50Hz/60Hz Rejection (87dB Minimum) Differential Input and Differential Reference with GND to VCC Common Mode Range 2ppm INL and No Missing Codes at 24 Bits 0.1ppm Offset and 2.5ppm Full-Scale Error 0.16ppm Noise No Latency: Digital Filter Settles in a Single Cycle. Internal Oscillator--No External Components Required 24-Bit ADC in Narrow SSOP-16 Package (SO-8 Footprint) Single Supply 2.7V to 5.5V Operation Low Supply Current (200A) and Auto Shutdown Pin Compatible with LTC2410
The LTC(R)2413 is a 2.7V to 5.5V simultaneous 50Hz/60Hz rejection micropower 24-bit differential analog to digital converter with an integrated oscillator, 2ppm INL and 0.16ppm RMS noise. It uses delta-sigma technology and provides single cycle settling time for multiplexed applications. Through a single pin, the LTC2413 can be configured for better than 87dB input differential mode rejection over the range of 49Hz to 61.2Hz (50Hz and 60Hz 2% simultaneously), or it can be driven by an external oscillator for a user defined rejection frequency. The internal oscillator requires no external frequency setting components. The converter accepts any external differential reference voltage from 0.1V to VCC for flexible ratiometric and remote sensing measurement configurations. The fullscale differential input range is from - 0.5VREF to 0.5VREF. The reference common mode voltage, VREFCM, and the input common mode voltage, VINCM, may be independently set anywhere within the GND to VCC range of the LTC2413. The DC common mode input rejection is better than 140dB. The LTC2413 communicates through a flexible 3-wire digital interface which is compatible with SPI and MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation. No Latency is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
APPLICATIO S
s s s s s s s s s s
Direct Sensor Digitizer Weight Scales Direct Temperature Measurement Gas Analyzers Strain-Gauge Transducers Instrumentation Data Acquisition Industrial Process Control 6-Digit DVMs Products for International Markets
TYPICAL APPLICATIO
2.7V TO 5.5V 1F 2 VCC LTC2413 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 3 4 5 6 REF + REF - IN + IN - GND SDO CS 12 11 SCK 13 FO 14
Measured Noise Rejection from 48Hz to 62.5Hz
-80 -85 MEASURED DATA CALCULATED DATA VCC = 5V REF + = 5V REF - = GND VINCM = 2.5V VIN(P-P) = 5V TA = 25C
NORMAL MODE REECTION (dB)
-90 -95 -100 -105 -110 -115 -120 48 50
= EXTERNAL CLOCK SOURCE = INTERNAL OSC/ SIMULTANEOUS 50Hz/60Hz REJECTION
3-WIRE SPI INTERFACE
1, 7, 8, 9, 10, 15, 16
2413 TA01
U
52 54 56 58 60 INPUT FREQUENCY (Hz) 62
2413 TA02
U
U
1
LTC2413
ABSOLUTE
(Notes 1, 2)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW GND VCC REF + REF - IN + IN - GND GND 1 2 3 4 5 6 7 8 16 GND 15 GND 14 FO 13 SCK 12 SDO 11 CS 10 GND 9 GND
Supply Voltage (VCC) to GND .......................- 0.3V to 7V Analog Input Pins Voltage to GND .................................... - 0.3V to (VCC + 0.3V) Reference Input Pins Voltage to GND .................................... - 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ - 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... - 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2413C ............................................... 0C to 70C LTC2413I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC2413CGN LTC2413IGN GN PART MARKING 2413 2413I
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 95C/W
Consult factory for parts specified with wider operating temperature ranges.
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity CONDITIONS 0.1V VREF VCC, -0.5 * VREF VIN 0.5 * VREF, (Note 5) 4.5V VCC 5.5V, REF+ = 2.5V, REF- = GND, VINCM = 1.25V, (Note 6) 5V VCC 5.5V, REF+ = 5V, REF- = GND, VINCM = 2.5V, (Note 6) REF+ = 2.5V, REF- = GND, VINCM = 1.25V, (Note 6) 2.5V REF+ VCC, REF- = GND, GND IN+ = IN- VCC, (Note 13) 2.5V REF+ VCC, REF- = GND, GND IN+ = IN- VCC 2.5V REF+ VCC, REF- = GND, IN+ = 0.75 * REF+, IN- = 0.25 * REF+ 2.5V REF+ VCC, REF- = GND, IN+ = 0.75 * REF+, IN- = 0.25 * REF+ 2.5V REF+ VCC, REF- = GND, IN+ = 0.25 * REF+, IN- = 0.75 * REF+ 2.5V REF+ VCC, REF- = GND, IN+ = 0.25 * REF+, IN- = 0.75 * REF+ 4.5V VCC 5.5V, REF+ = 2.5V, REF- = GND, VINCM = 1.25V 5V VCC 5.5V, REF+ = 5V, REF- = GND, VINCM = 2.5V REF+ = 2.5V, REF- = GND, VINCM = 1.25V 5V VCC 5.5V, REF+ = 5V, VREF- = GND, GND IN- = IN+ 5V, (Note 12)
q q q q q
ELECTRICAL CHARACTERISTICS
MIN 24
TYP 1 2 0.5 10 2.5 0.03 2.5 0.03 3 3 4 0.8
MAX
UNITS Bits ppm of VREF ppm of VREF ppm of VREF V nV/C
14 2.5
Offset Error Offset Error Drift Positive Full-Scale Error Positive Full-Scale Error Drift Negative Full-Scale Error Negative Full-Scale Error Drift Total Unadjusted Error
12
ppm of VREF ppm of VREF/C
12
ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF ppm of VREF VRMS
Output Noise
2
U
W
U
U
WW
W
LTC2413
CO VERTER CHARACTERISTICS
PARAMETER Input Common Mode Rejection DC Input Common Mode Rejection 49Hz to 61.2Hz Input Normal Mode Rejection 49Hz to 61.2Hz Input Normal Mode Rejection External Clock fEOSC/2560 14% Input Normal Mode Rejection External Clock fEOSC/2560 4% Reference Common Mode Rejection DC Power Supply Rejection, DC Power Supply Rejection Simultaneous 50Hz/60Hz 2% CONDITIONS
- CC, REF = GND, GND IN- = IN+ VCC 2.5V REF+ VCC, REF- = GND, GND IN- = IN+ VCC, (Note 7)
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 3, 4)
MIN
q q q q q q
A ALOG I PUT A D REFERE CE The q denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (Note 3)
SYMBOL IN+ IN- VIN REF+ REF- VREF CS (IN+) CS (IN-) CS CS (REF+) (REF-) (IN+) (REF+) PARAMETER Absolute/Common Mode IN+ Voltage Absolute/Common Mode IN- Voltage Input Differential Voltage Range (IN+ - IN-) Absolute/Common Mode REF+ Voltage Absolute/Common Mode REF- Voltage Reference Differential Voltage Range (REF+ - REF-) IN+ Sampling Capacitance IN- Sampling Capacitance REF+ Sampling Capacitance REF- Sampling Capacitance IN+ DC Leakage Current IN- DC Leakage Current REF+ DC Leakage Current REF- DC Leakage Current CS = VCC, IN+ CS = VCC, IN- = GND = GND
q q q q
IDC_LEAK IDC_LEAK
IDC_LEAK (IN-) IDC_LEAK (REF-)
U
U
U
U
TYP 140
MAX
UNITS dB dB dB dB
2.5V REF+ V
130 140 87 87 110 130
(Note 7) External Oscillator External Oscillator 2.5V REF+ VCC, GND REF- 2.5V, VREF = 2.5V, IN- = IN+ = GND REF+ = 2.5V, REF- = GND, IN- = IN+ = GND = GND, IN- = IN+ = GND, (Note 7) REF+ = 2.5V, REF-
140 140 120 120
dB dB dB dB
U
CONDITIONS
q q q q q q
MIN GND - 0.3V GND - 0.3V -VREF/2 0.1 GND 0.1
TYP
MAX VCC + 0.3V VCC + 0.3V VREF/2 VCC VCC - 0.1V VCC
UNITS V V V V V V pF pF pF pF
18 18 18 18 -10 -10 -10 -10 1 1 1 1 10 10 10 10
nA nA nA nA
CS = VCC, REF+ = 5V CS = VCC, REF- = GND
3
LTC2413
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK Hi-Z Output Leakage SDO (Note 8) IO = -800A IO = 1.6mA IO = -800A (Note 9) IO = 1.6mA (Note 9)
q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS 2.7V VCC 5.5V 2.7V VCC 3.3V 4.5V VCC 5.5V 2.7V VCC 5.5V 2.7V VCC 5.5V (Note 8) 2.7V VCC 3.3V (Note 8) 4.5V VCC 5.5V (Note 8) 2.7V VCC 5.5V (Note 8) 0V VIN VCC 0V VIN VCC (Note 8)
q q q q q q
POWER REQUIRE E TS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
q
4
UW
U
U
MIN 2.5 2.0
TYP
MAX
UNITS V V
0.8 0.6 2.5 2.0 0.8 0.6 -10 -10 10 10 VCC - 0.5V 0.4 VCC - 0.5V 0.4 -10 10 10 10
V V V V V V A A pF pF V V V V A
MIN 2.7
TYP
MAX 5.5
UNITS V A A
CS = 0V (Note 11) CS = VCC (Note 11)
q q
200 20
300 30
LTC2413
TI I G CHARACTERISTICS
SYMBOL fEOSC tHEO tLEO tCONV fISCK DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time Internal SCK Frequency Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 32-Bit Data Output Time External SCK 32-Bit Data Output Time CS to SDO Low Z CS to SDO Hi-Z CS to SCK CS to SCK SCK to SDO Valid SDO Hold After SCK SCK Set-Up Before CS SCK Hold After CS (Note 5) (Note 9) (Note 8) FO = 0V External Oscillator (Note 10) Internal Oscillator (Note 9) External Oscillator (Notes 9, 10) (Note 9) (Note 8) (Note 8) (Note 8) Internal Oscillator (Notes 9, 11) External Oscillator (Notes 9, 10) (Note 8)
q q q q q q q q q q q q q q q
The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3)
CONDITIONS
q q q q q
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREF = REF + - REF -, VREFCM = (REF + + REF -)/2; VIN = IN + - IN -, VINCM = (IN + + IN -)/2. Note 4: FO pin tied to GND or to external conversion clock source with fEOSC = 139800Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
UW
MIN 2.56 0.25 0.25
TYP
MAX 2000 390 390
UNITS kHz s s ms ms kHz kHz
146.71 20510/fEOSC (in kHz) 17.5 fEOSC/8 45 250 250 1.80 1.83 1.86 256/fEOSC (in kHz) 32/fESCK (in kHz) 0 0 0 50 220 15 50 50 200 200 200 55 2000
% kHz ns ns ms ms ms ns ns ns ns ns ns ns ns
Note 7: FO = 0V (internal oscillator) or fEOSC = 139800Hz 2% (external oscillator). Note 8: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 9: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. Note 10: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses the internal oscillator. FO = 0V. Note 12: The output noise includes the contribution of the internal calibration operations. Note 13: Guaranteed by design and test correlation.
5
LTC2413 TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error vs Temperature (VCC = 5V, VREF = 5V)
1.5 1.0
TUE (ppm OF VREF)
TUE (ppm OF VREF)
TUE (ppm OF VREF)
0.5 0 -0.5 -1.0 VCC = 5V REF + = 5V REF - = GND VREF = 5V VINCM = 2.5V FO = GND TA = 90C TA = 25C TA = -45C
-1.5 -2.5 -2 -1.5 -1 -0.5 0 0.5 VIN (V)
1
Integral Nonlinearity vs Temperature (VCC = 5V, VREF = 5V)
1.5 1.0
INL ERROR (ppm OF VREF)
INL ERROR (ppm OF VREF)
0.5 0 -0.5 -1.0
0.5 0 VCC = 5V REF + = 2.5V REF - = GND VREF = 2.5V VINCM = 1.25V FO = GND -1 -0.5
TA = 25C TA = 90C
INL ERROR (ppm OF VREF)
VCC = 5V REF + = 5V REF - = GND VREF = 5V VINCM = 2.5V FO = GND
TA = -45C 1.0 TA = 25C TA = -45C
-1.5 -2.5 -2 -1.5 -1 -0.5 0 0.5 VIN (V)
1
Noise Histogram (Output Rate = 6.83Hz, VCC = 5V, VREF = 5V)
12 10 8 6 4 2 0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 OUTPUT CODE (ppm OF VREF) 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF - = GND IN + = 2.5V IN - = 2.5V FO = GND TA = 25C GAUSSIAN DISTRIBUTION m = 0.105ppm = 0.153ppm 12 10 8 6 4 2
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
6
UW
1.5 2
2413 G01
Total Unadjusted Error vs Temperature (VCC = 5V, VREF = 2.5V)
1.5 1.0 0.5 0 TA = 90C TA = 25C TA = -45C VCC = 5V REF + = 2.5V REF - = GND VREF = 2.5V VINCM = 1.25V FO = GND 10 8 6 4 2 0 -2 -4 -6 -8 2.5 -1.5 -1 -0.5 0 VIN (V) 0.5 1
2413 G02
Total Unadjusted Error vs Temperature (VCC = 2.7V, VREF = 2.5V)
TA = 90C TA = 25C VCC = 2.7V REF + = 2.5V REF - = GND VREF = 2.5V VINCM = 1.25V FO = GND -1 -0.5 0 VIN (V)
-0.5 -1.0
TA = -45C
-10
0.5
1
2413 G03
Integral Nonlinearity vs Temperature (VCC = 5V, VREF = 2.5V)
1.5 10 8 6 4 2 0 -2 -4 -6 -8 0 VIN (V) 0.5 1
2413 G05
Integral Nonlinearity vs Temperature (VCC = 2.7V, VREF = 2.5V)
VCC = 2.7V VREF = 2.5V REF + = 2.5V VINCM = 1.25V REF - = GND FO = GND
TA = 90C
-0.5 -1.0 -1.5
TA = 90C TA = 25C TA = -45C
1.5
2
2.5
-10
-1
-0.5
0 VIN (V)
0.5
1
2413 G06
2413 G04
Noise Histogram (Output Rate = 22.5Hz, VCC = 5V, VREF = 5V)
10,000 CONSECUTIVE READINGS VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF - = GND IN + = 2.5V IN - = 2.5V FO = 460800Hz TA = 25C GAUSSIAN DISTRIBUTION m = 0.067ppm = 0.151ppm 12 10 8 6 4 2
Noise Histogram (Output Rate = 52.5Hz, VCC = 5V, VREF = 5V)
10,000 CONSECUTIVE READINGS VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF - = GND IN + = 2.5V IN - = 2.5V FO = 1075200Hz TA = 25C GAUSSIAN DISTRIBUTION m = 8.285ppm = 0.311ppm
0.8
0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 OUTPUT CODE (ppm OF VREF)
0.8
0 -9.8 -9.4 -9 -8.6 -8.2 -7.8 -7.4 -7 -6.6 OUTPUT CODE (ppm OF VREF)
2413 G09
2413 G07
2413 G08
LTC2413 TYPICAL PERFOR A CE CHARACTERISTICS
Noise Histogram (Output Rate = 6.83Hz VCC = 5V, VREF = 2.5V)
12 10 8 6 4 2 0 -1.6 10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF - = GND IN + = 1.25V IN - = 1.25V FO = GND TA = 25C GAUSSIAN DISTRIBUTION m = 0.033ppm = 0.293ppm 12 10 8 6 4 2 0 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 OUTPUT CODE (ppm OF VREF)
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
-0.8 0 0.8 OUTPUT CODE (ppm OF VREF)
Noise Histogram (Output Rate = 6.83Hz VCC = 2.7V, VREF = 2.5V)
12 10 8 6 4 2 0 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 OUTPUT CODE (ppm OF VREF) 10,000 CONSECUTIVE READINGS VCC = 2.7V VREF = 2.5V VIN = 0V REF + = 2.5V REF - = GND IN + = 1.25V IN - = 1.25V FO = GND TA = 25C GAUSSIAN DISTRIBUTION m = 0.079ppm = 0.298ppm 12 10 8 6 4 2
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
NUMBER OF READINGS (%)
Long-Term Noise Histogram (Time = 60 Hrs, VCC = 5V, VREF = 5V)
12 10 8 6 4 2 GAUSSIAN DISTRIBUTION m = 0.101837ppm = 0.154515ppm ADC CONSECUTIVE READINGS VCC = 5V VREF = 5V VIN = 0V REF + = 5V REF - = GND IN + = 2.5V IN - = 2.5V FO = GND TA = 25C 0.8 1.0 0.8
ADC READING (ppm OF VREF)
NUMBER OF READINGS (%)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 VCC = 5V TA = 25C IN + = 2.5V VREF = 5V REF + = 5V IN - = 2.5V VIN = 0V REF - = GND FO = GND 5 10 15 20 25 30 35 40 45 50 55 60 TIME (HOURS)
2413 G17
RMS NOISE (ppm OF VREF)
0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 OUTPUT CODE (ppm OF VREF)
UW
1.6
2413 G10
Noise Histogram (Output Rate = 22.5Hz, VCC = 5V, VREF = 2.5V)
10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF - = GND IN + = 1.25V IN - = 1.25V FO = 460800Hz TA = 25C GAUSSIAN DISTRIBUTION m = 0.014ppm = 0.292ppm 12 10 8 6 4 2
Noise Histogram (Output Rate = 52.5Hz, VCC = 5V, VREF = 2.5V)
10,000 CONSECUTIVE READINGS VCC = 5V VREF = 2.5V VIN = 0V REF + = 2.5V REF - = GND IN + = 1.25V IN - = 1.25V FO = 1075200Hz TA = 25C GAUSSIAN DISTRIBUTION m = 3.852ppm = 0.326ppm
1.6
0 -5.5 -5.1 -4.7 -4.3 -3.9 -3.5 -3.1 -2.7 -2.3 OUTPUT CODE (ppm OF VREF)
2413 G12
2413 G11
Noise Histogram (Output Rate = 22.5Hz, VCC = 2.7V, VREF = 2.5V)
10,000 CONSECUTIVE READINGS VCC = 2.7V VREF = 2.5V VIN = 0V REF + = 2.5V REF - = GND IN + = 1.25V IN - = 1.25V FO = 460800Hz TA = 25C GAUSSIAN DISTRIBUTION m = 0.177ppm = 0.297ppm 10
Noise Histogram (Output Rate = 52.5Hz, VCC = 2.7V, VREF = 2.5V)
10,000 CONSECUTIVE 9 READINGS V = 2.7V 8 VCC = 2.5V REF 7 VIN = 0V REF + = 2.5V 6 REF - = GND IN + = 1.25V 5 IN - = 1.25V 4 FO = 1075200Hz TA = 25C 3 2 1 GAUSSIAN DISTRIBUTION m = 3.714ppm = 1.295ppm
1.6
0 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 OUTPUT CODE (ppm OF VREF)
1.6
0 -10 -8.5 -7 -5.5 -4 -2.5 -1 0.5 OUTPUT CODE (ppm OF VREF)
2
2413 G13
2413 G14
2413 G15
Consecutive ADC Readings vs Time
0.5
RMS Noise vs Input Differential Voltage
VCC = 5V VREF = 5V REF + = 5V REF - = GND VINCM = 2.5V FO = GND TA = 25C
0.6
0.4
0.3
0.2
0.1
0 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 INPUT DIFFERENTIAL VOLTAGE (V)
2.5
2413 G16
2413 G18
7
LTC2413 TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs VINCM
850 825 800
RMS NOISE (nV)
RMS NOISE (nV)
775 750 725 700 675
VCC = 5V REF + = 5V REF - = GND VREF = 5V IN + = VINCM IN - = VINCM VIN = 0V FO = GND TA = 25C
775 750 725 700 675 650 -50
RMS NOISE (nV)
650 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VINCM (V)
2413 G19
RMS Noise vs VREF
850 825 800
RMS NOISE (nV)
OFFSET ERROR (ppm OF VREF)
775 750 725 700 675 650 0
0.1 0 -0.1 -0.2 VCC = 5V REF + = 5V REF - = GND VREF = 5V IN + = VINCM IN - = VINCM VIN = 0V FO = GND TA = 25C
OFFSET ERROR (ppm OF VREF)
VCC = 5V REF - = GND IN + = GND IN - = GND FO = GND TA = 25C
0.5
1
1.5
2 2.5 3 VREF (V)
3.5
Offset Error vs VCC
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 2.7 0.3 0.2 0.1 0 -0.1 -0.2 -0.3
+FULL-SCALE ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
REF + = 2.5V REF - = GND VREF = 2.5V IN + = GND IN - = GND FO = GND TA = 25C 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5
8
UW
4 4.5
2413 G22 2413 G25
RMS Noise vs Temperature (TA)
850 825 800 VCC = 5V REF + = 5V REF - = GND IN + = 2.5V IN - = 2.5V VIN = 0V FO = GND 850 825 800 775 750 725 700 675 -25 0 25 50 TEMPERATURE (C) 75 100
2413 G20
RMS Noise vs VCC
REF + = 2.5V REF - = GND VREF = 2.5V IN + = GND IN - = GND FO = GND TA = 25C
650 2.7
3.1
3.5
3.9 4.3 VCC (V)
4.7
5.1
5.5
2413 G21
Offset Error vs VINCM
0.3 0.2 0.3 0.2 0.1 0 -0.1 -0.2
Offset Error vs Temperature (TA)
VCC = 5V REF + = 5V REF - = GND IN + = 2.5V IN - = 2.5V VIN = 0V FO = GND -25 0 25 50 TEMPERATURE (C) 75 100
2413 G24
5
-0.3 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VINCM (V)
2413 G23
-0.3 -50
Offset Error vs VREF
3 2 1 0 -1 -2
+ Full-Scale Error vs Temperature (TA)
VCC = 5V REF - = GND IN + = GND IN - = GND FO = GND TA = 25C 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 5
VCC = 5V REF + = 5V REF - = GND IN + = 2.5V IN - = GND FO = GND 0 15 30 45 60 TEMPERATURE (C) 75 90
-3 -45 -30 -15
2413 G26
2413 G27
LTC2413 TYPICAL PERFOR A CE CHARACTERISTICS
+ Full-Scale Error vs VCC
3 +FULL-SCALE ERROR (ppm OF VREF) 2 1 0 -1 -2 -3 2.7 +FULL-SCALE ERROR (ppm OF VREF) 3 2 1 0 -1 -2 -3 -FULL-SCALE ERROR (ppm OF VREF)
REF + = 2.5V REF - = GND VREF = 2.5V IN + = 1.25V IN - = GND FO = GND TA = 25C 3.1 3.5 3.9 4.3 VCC (V) 4.7 5.1 5.5
- Full-Scale Error vs VCC
3 -FULL-SCALE ERROR (ppm OF VREF) -FULL-SCALE ERROR (ppm OF VREF) 2 1 0 -1 -2 -3 2.7 REF + = 2.5V REF - = GND VREF = 2.5V IN + = GND IN - = 1.25V FO = GND TA = 25C 3 2 1 0 -1 -2 -3
REJECTION (dB)
3.1
3.5
3.9 4.3 VCC (V)
4.7
PSRR vs Frequency at VCC
0 -20 -40
REJECTION (dB)
REJECTION (dB)
REJECTION (dB)
-60 -80 -100 -120 -140
VCC = 4.1VDC 1.4V REF + = 2.5V REF - = GND IN + = GND IN - = GND FO = GND TA = 25C
0 20 40 60 80 100 120 140 160 180 200 220 FREQUENCY AT VCC (Hz)
2413 G34
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2413 G28
+ Full-Scale Error vs VREF
3 2 1 0 -1 -2
- Full-Scale Error vs Temperature (TA)
VCC = 5V REF + = 5V REF - = GND IN + = GND IN - = 2.5V FO = GND
VCC = 5V REF + = VREF REF - = GND IN + = 0.5 * REF + IN - = GND FO = GND TA = 25C 0 0.5 1 1.5 2 2.5 3 VREF (V) 3.5 4 4.5 5
-3 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
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2413 G29
2413 G30
- Full-Scale Error vs VREF
0 VCC = 5V REF + = VREF REF - = GND IN + = GND IN - = 0.5 * REF + FO = GND TA = 25C -20 -40 -60 -80 -100 -120
PSRR vs Frequency at VCC
VCC = 4.1VDC 1.4V REF + = 2.5V REF - = GND IN + = GND IN - = GND FO = GND TA = 25C
5.1
5.5
0
0.5
1
1.5
2 2.5 3 VREF (V)
3.5
4
4.5
5
-140 0.01
0.1 1 10 FREQUENCY AT VCC (Hz)
100
2413 G33
2413 G31
2413 G32
PSRR vs Frequency at VCC
0 -20 -40 -60 -80 -100 -120 -140 REF + = 2.5V REF - = GND IN + = GND IN - = GND FO = GND TA = 25C 0 -20 -40 -60 -80 -100 -120
PSRR vs Frequency at VCC
VCC = 4.1VDC 0.7V REF + = 2.5V REF - = GND IN + = GND IN - = GND FO = GND TA = 25C
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10
100 1k 10k 100k FREQUENCY AT VCC (Hz)
1M
-140 13900
13950 14000 14050 FREQUENCY AT VCC (Hz)
14100
2413 G36
2413 G35
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LTC2413 TYPICAL PERFOR A CE CHARACTERISTICS
Conversion Current vs Temperature (TA)
220 210 FO = GND CS = GND SCK = NC SDO = NC 1100 1000
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
VCC = 5.5V
200 190 180 VCC = 2.7V 170 160 -45 -30 -15 VCC = 4.1V
0 15 30 45 60 TEMPERATURE (C)
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GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground pins internally connected for optimum ground current flow and VCC decoupling. Connect each one of these pins to a ground plane through a low impedance connection. All seven pins must be connected to ground for proper operation. VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 1) with a 10F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. REF + (Pin 3), REF - (Pin 4): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF +, is maintained more positive than the reference negative input, REF -, by at least 0.1V. IN+ (Pin 5), IN- (Pin 6): Differential Analog Input. The voltage on these pins can have any value between GND - 0.3V and VCC + 0.3V. Within these limits, the converter bipolar input range (VIN = IN+ - IN-) extends from -0.5 * (VREF) to 0.5 * (VREF). Outside this input range, the converter produces unique overrange and underrange output codes. CS (Pin 11): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion, the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 12): Three-State Digital Output. During the Data Output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = VCC), the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface clock during the Data Output period. A weak internal pullup is automatically activated in Internal Serial Clock Operation mode. The Serial Clock Operation mode is determined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. FO (Pin 14): Frequency Control Pin. Digital input that controls the ADC's notch frequencies and conversion time. When the FO pin is connected to GND (FO = 0V), the converter uses its internal oscillator and the digital filter rejects 50Hz and 60Hz simultaneously. When the FO pin is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its system clock and the digital filter has 87dB minimum rejection in the range fEOSC/2560 14% and 110dB minimum rejection at fEOSC/2560 4%.
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75 90
2413 G37
Conversion Current vs Output Data Rate
VCC = 5V REF + = 5V REF - = GND IN + = GND IN - = GND TA = 25C FO = EXTERNAL OSC CS = GND SCK = NC SDO = NC 23 22 21 20 19
Sleep Current vs Temperature (TA)
FO = GND CS = VCC SCK = NC SDO = NC VCC = 5.5V VCC = 4.1V
900 800 700 600 500 400 300 200 100 0
VCC = 2.7V 18 17 16 -45 -30 -15
10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) 2413 G38
0 15 30 45 60 TEMPERATURE (C)
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2413 G39
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LTC2413
FU CTIO AL BLOCK DIAGRA
VCC GND AUTOCALIBRATION AND CONTROL
IN + IN -
+ -

ADC SERIAL INTERFACE DECIMATING FIR
REF
REF + -
-+
DAC
Figure 1. Functional Block Diagram
TEST CIRCUITS
SDO
SDO
1.69k
CLOAD = 20pF
CLOAD = 20pF
Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z
2413 TA03
APPLICATIO S I FOR ATIO
CONVERTER OPERATION Converter Operation Cycle
The LTC2413 is a low power, delta-sigma analog-todigital converter with an easy to use 3-wire serial interface. Its operation is made up of three states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock (SCK) and chip select (CS). Initially, the LTC2413 performs a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is reduced by an order of magnitude. The part remains in the sleep state as long as CS is HIGH. The conversion result is held indefinitely in a static shift register while the converter is in the sleep state.
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INTERNAL OSCILLATOR FO (INT/EXT) SDO SCK CS
2413 FD
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VCC 1.69k
Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z
2413 TA04
CONVERT
SLEEP
FALSE
CS = LOW AND SCK TRUE DATA OUTPUT
2413 F02
Figure 2. LTC2413 State Transition Diagram
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LTC2413
APPLICATIO S I FOR ATIO
Once CS is pulled LOW, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corresponds to the conversion just performed. This result is shifted out on the serial data out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the user to reliably latch data on the rising edge of SCK (see Figure 3). The data output state is concluded once 32 bits are read out of the ADC or when CS is brought HIGH. The device automatically initiates a new conversion and the cycle repeats. Through timing control of the CS and SCK pins, the LTC2413 offers several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of operation are described in detail in the Serial Interface Timing Modes section. Conversion Clock A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter (commonly implemented as a sinc or comb filter). For high resolution, low frequency applications, this filter is designed to simultaneously reject line frequencies of 50Hz and 60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter system clock. The LTC2413 incorporates a highly accurate on-chip oscillator. This eliminates the need for external frequency setting components such as crystals or oscillators. The LTC2413 achieves a minimum of 87dB over the range of 49Hz to 61.2Hz. Ease of Use The LTC2413 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing multiple analog voltages is easy.
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The LTC2413 performs offset and full-scale calibrations in every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2413 automatically enters an internal reset state when the power supply voltage VCC drops below approximately 2.2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selection. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the VCC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a duration of approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the LTC2413 starts a normal conversion cycle and follows the succession of states described above. The first conversion result following POR is accurate within the specifications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range This converter accepts a truly differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF - pins covers the entire range from GND to VCC. For correct converter operation, the REF + pin must always be more positive than the REF - pin. The LTC2413 can accept a differential reference voltage from 0.1V to VCC. The converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. A decrease in reference voltage will not significantly improve the converter's effective resolution. On the other hand, a reduced reference voltage will improve the converter's overall INL performance. A reduced reference voltage will also improve the converter performance when operated with an external conversion clock (external FO signal) at substantially higher output data rates (see the Output Data Rate section).
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LTC2413
APPLICATIO S I FOR ATIO
Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN+ and IN- input pins extending from GND - 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2413 converts the bipolar differential input signal, VIN = IN+ - IN-, from - FS = - 0.5 * VREF to +FS = 0.5 * VREF where VREF = REF+ - REF-. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. Input signals applied to IN+ and IN- pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the IN+ and IN- pins without affecting the performance of the device. In the physical layout, it is important to maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/ Reference Current sections. In addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. A 1nA input leakage current will develop a 1ppm offset error on a 5k resistor if VREF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2413 serial output data stream is 32 bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 24 bits are the conversion result, MSB first. The remaining 5 bits are sub LSBs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. The third and fourth bits together are also used to indicate an underrange condition (the differential input voltage is below -FS) or an overrange condition (the differential input voltage is above +FS). Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the conversion and sleep states whenever the CS pin is LOW.
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This bit is HIGH during the conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is a dummy bit (DMY) and is always LOW. Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this bit is LOW. Bit 28 (fourth output bit) is the most significant bit (MSB) of the result. This bit in conjunction with Bit 29 also provides the underrange or overrange indication. If both Bit 29 and Bit 28 are HIGH, the differential input voltage is above +FS. If both Bit 29 and Bit 28 are LOW, the differential input voltage is below -FS. The function of these bits is summarized in Table 1.
Table 1. LTC2413 Status Bits
Input Range VIN 0.5 * VREF 0V VIN < 0.5 * VREF -0.5 * VREF VIN < 0V VIN < - 0.5 * VREF Bit 31 Bit 30 Bit 29 Bit 28 EOC DMY SIG MSB 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0
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Bits 28-5 are the 24-bit conversion result MSB first. Bit 5 is the least significant bit (LSB). Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may be included in averaging or discarded without loss of resolution. Data is shifted out of the SDO pin under control of the serial clock (SCK), see Figure 3. Whenever CS is HIGH, SDO remains high impedance and any externally generated SCK clock pulses are ignored by the internal data out shift register. In order to shift the conversion result out of the device, CS must first be driven LOW. EOC is seen at the SDO pin of the device once CS is pulled LOW. EOC changes real time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising edge of SCK. Bit 30 is shifted out of the device on the first falling edge of SCK. The final data bit (Bit 0) is shifted out on the falling edge of the 31st SCK and may be latched
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LTC2413
APPLICATIO S I FOR ATIO
on the rising edge of the 32nd SCK pulse. On the falling edge of the 32nd SCK pulse, SDO goes HIGH indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. As long as the voltage on the IN+ and IN- pins is maintained within the - 0.3V to (VCC + 0.3V) absolute maximum operating range, a conversion result is generated for any differential input voltage VIN from -FS = -0.5 * VREF to +FS = 0.5 * VREF. For differential input voltages greater than +FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages below -FS, the conversion result is clamped to the value corresponding to -FS - 1LSB.
CS
BIT 31 SDO Hi-Z EOC
BIT 30 "0"
BIT 29 SIG
SCK
1 SLEEP
2
Figure 3. Output Data Timing Table 2. LTC2413 Output Data Format
Differential Input Voltage VIN * VIN* 0.5 * VREF** 0.5 * VREF** - 1LSB 0.25 * VREF** 0.25 * VREF** - 1LSB 0 -1LSB - 0.25 * VREF** - 0.25 * VREF** - 1LSB - 0.5 * VREF** VIN* < -0.5 * VREF** Bit 31 EOC 0 0 0 0 0 0 0 0 0 0 Bit 30 DMY 0 0 0 0 0 0 0 0 0 0 Bit 29 SIG 1 1 1 1 1 0 0 0 0 0 Bit 28 MSB 1 0 0 0 0 1 1 1 1 0 Bit 27 0 1 1 0 0 1 1 0 0 1 Bit 26 0 1 0 1 0 1 0 1 0 1 Bit 25 0 1 0 1 0 1 0 1 0 1 ... ... ... ... ... ... ... ... ... ... ... Bit 0 0 1 0 1 0 1 0 1 0 1
*The differential input voltage VIN = IN+ - IN-. **The differential reference voltage VREF = REF+ - REF-.
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Simultaneous Frequency Rejection The LTC2413 internal oscillator provides better than 87dB normal mode rejection over the range of 49Hz to 61.2Hz as shown in Figure 4. For this simultaneous 50Hz/60Hz rejection, FO should be connected to GND. When a fundamental rejection frequency different from the range 49Hz to 61.2Hz is required or when the converter must be sychronized with an outside source, the LTC2413 can operate with an external conversion clock. The conveter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. The frequency fEOSC of the external signal must be at least 2560Hz to be detected. The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods, tHEO and tLEO, are observed.
BIT 28 MSB BIT 27 BIT 5 LSB24 BIT 0 3 4 5 26 27 32 CONVERSION
2413 F03
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DATA OUTPUT
LTC2413
APPLICATIO S I FOR ATIO
While operating with an external conversion clock of a frequency fEOSC, the LTC2413 provides better than 110dB normal mode rejection in a frequency range fEOSC/2560 4%. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 5. Whenever an external clock is not present at the FO pin the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2413 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. If the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the data output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. Table 3 summarizes the duration of each state and the achievable output data rate as a function of FO. SERIAL INTERFACE PINS The LTC2413 transmits the conversion results and receives the start of conversion command through a synchronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result.
Table 3. LTC2413 State Duration
State CONVERT Operating Mode Internal Oscillator External Oscillator FO = LOW Simultaneous 50Hz/60Hz Rejection FO = External Oscillator with Frequency fEOSC kHz (fEOSC/2560 Rejection) FO = LOW (Internal Oscillator) FO = External Oscillator with Frequency fEOSC kHz External Serial Clock with Frequency fSCK kHz Duration 147ms, Output Data Rate 6.8 Readings/s 20510/fEOSCs, Output Data Rate fEOSC/20510 Readings/s
NORMAL MODE REECTION RATIO (dB)
NORMAL MODE REJECTION (dB)
SLEEP DATA OUTPUT Internal Serial Clock
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-80 -90 -100 -100 -120 -130 -140 48 50 52 54 56 58 60 62 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2413 F04
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Figure 4. LTC2413 Normal Mode Rejection When Using an Internal Oscillator
-80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -12 -8 -4 0 4 8 12 DIFFERENTIAL INPUT SIGNAL FREQUENCY DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
2413 F05
Figure 5. LTC2413 Normal Mode Rejection When Using an External Oscillator of Frequency fEOSC
As Long As CS = HIGH Until CS = LOW and SCK As Long As CS = LOW But Not Longer Than 1.83ms (32 SCK cycles) As Long As CS = LOW But Not Longer Than 256/fEOSCms (32 SCK cycles) As Long As CS = LOW But Not Longer Than 32/fSCKms (32 SCK cycles)
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APPLICATIO S I FOR ATIO
Serial Clock Input/Output (SCK) The serial clock signal present on SCK (Pin 13) is used to synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2413 creates its own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation, the SCK pin is used as input. The internal or external SCK mode is selected on power-up and then reselected every time a HIGH-to-LOW transition is detected at the CS pin. If SCK is HIGH or floating at powerup or during this transition, the converter enters the internal SCK mode. If SCK is LOW at power-up or during this transition, the converter enters the external SCK mode. Serial Data Output (SDO) The serial data output pin, SDO (Pin 12), provides the result of the last conversion as a serial bit stream (MSB first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the conversion and sleep states. When CS (Pin 11) is HIGH, the SDO driver is switched to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CS = LOW. Chip Select Input (CS) The active LOW chip select, CS (Pin 11), is used to test the conversion status and to enable the data output transfer as described in the previous sections.
Table 4. LTC2413 Interface Timing Modes
Configuration External SCK, Single Cycle Conversion External SCK, 2-Wire I/O Internal SCK, Single Cycle Conversion Internal SCK, 2-Wire I/O, Continuous Conversion Internal SCK, Autostart Conversion SCK Source External External Internal Internal Internal Conversion Cycle Control CS and SCK SCK CS Continuous CEXT Data Output Control CS and SCK SCK CS Internal Internal Connection and Waveforms Figures 6, 7 Figure 8 Figures 9, 10 Figure 11 Figure 12
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In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2413 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., after the first rising edge of SCK occurs with CS = LOW). Finally, CS can be used to control the free-running modes of operation, see Serial Interface Timing Modes section. Grounding CS will force the ADC to continuously convert at the maximum output rate selected by FO. Tying a capacitor to CS will reduce the output rate and power dissipation by a factor proportional to the capacitor's value, see Figures 13 to 15. SERIAL INTERFACE TIMING MODES The LTC2413's 3-wire interface is SPI and MICROWIRE compatible. This interface offers several flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle conversion and autostart. The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW) or an external oscillator connected to the FO pin. Refer to Table 4 for a summary. External Serial Clock, Single Cycle Operation (SPI/MICROWIRE Compatible) This timing mode uses an external serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 6.
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APPLICATIO S I FOR ATIO
The serial clock mode is selected on the falling edge of CS. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CS, the device automatically enters the low power sleep state once the conversion is complete. When the device is in the sleep state (EOC = 0), its conversion result is held in an internal static shift register. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. Data is shifted out the SDO pin on each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. On the 32nd falling edge of SCK, the device begins a new conversion. SDO goes HIGH (EOC = 1) indicating a conversion is in progress. At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
2.7V TO 5.5V 1F 2 VCC LTC2413 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 3 4 5 6 REF + REF - IN + IN - GND SDO CS 12 11 SCK 13 3-WIRE SPI INTERFACE FO 14 = EXTERNAL OSCILLATOR = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION
CS TEST EOC SDO Hi-Z Hi-Z TEST EOC TEST EOC
BIT 31 EOC
BIT 30
SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2413 F06
Figure 6. External Serial Clock, Single Cycle Operation
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As described above, CS may be pulled LOW at any time in order to monitor the conversion status. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first rising edge and the 32nd falling edge of SCK, see Figure 7. On the rising edge of CS, the device aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. External Serial Clock, 2-Wire I/O This timing mode utilizes a 2-wire serial I/O interface. The conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 8. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 0.5ms after VCC exceeds 2.2V. The level applied to SCK at this time determines if SCK is internal or external. SCK must be driven LOW prior to the end of POR in order to enter the external serial clock timing mode.
1, 7, 8, 9, 10, 15, 16 BIT 29 SIG BIT 28 MSB BIT 27 BIT 26 BIT 5 LSB BIT 0 SUB LSB Hi-Z
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2.7V TO 5.5V 1F 2 VCC LTC2413 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 3 4 5 6 REF + REF - IN + IN - GND SDO CS 12 11 SCK 13 3-WIRE SPI INTERFACE FO 14 = EXTERNAL OSCILLATOR = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION BIT 31 EOC Hi-Z Hi-Z Hi-Z BIT 30 BIT 29 SIG BIT 28 MSB Hi-Z BIT 27 BIT 9 BIT 8 TEST EOC DATA OUTPUT CONVERSION
2413 F07
CS TEST EOC TEST EOC
BIT 0 SDO EOC
SCK (EXTERNAL) SLEEP CONVERSION DATA OUTPUT SLEEP
Figure 7. External Serial Clock, Reduced Data Output Length
Since CS is tied LOW, the end-of-conversion (EOC) can be continuously monitored at the SDO pin during the convert and sleep states. EOC may be used as an interrupt to an external controller indicating the conversion result is ready. EOC = 1 while the conversion is in progress and EOC = 0 once the conversion enters the low power sleep state. On the falling edge of EOC, the conversion result is loaded into an internal static shift register. The device remains in the sleep state until the first rising edge of SCK. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising edge of SCK. EOC can be latched on the first rising edge of SCK. On the 32nd falling edge of SCK, SDO goes HIGH (EOC = 1) indicating a new conversion has begun. Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 9. In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled HIGH prior to the falling edge of CS. The device will not
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enter the internal serial clock mode if SCK is driven LOW on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to prevent the device from exiting the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of tEOCtest is 26s if the device is using its internal oscillator (F0 = logic LOW). If FO is driven by an external oscillator of frequency fEOSC,
LTC2413
APPLICATIO S I FOR ATIO U
2.7V TO 5.5V 1F 2 VCC LTC2413 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 3 4 5 6 REF + REF - IN + IN - GND SDO CS 12 11 SCK 13 2-WIRE I/O FO 14 = EXTERNAL OSCILLATOR = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION 1, 7, 8, 9, 10, 15, 16 BIT 29 SIG BIT 28 MSB BIT 27 BIT 26 BIT 5 LSB24 BIT 0 DATA OUTPUT CONVERSION
2413 F08
CS
SDO
SCK (EXTERNAL) CONVERSION SLEEP
BIT 31 EOC
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2413 F09
Figure 9. Internal Serial Clock, Single Cycle Operation
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EOC
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BIT 31
BIT 30
Figure 8. External Serial Clock, CS = 0 Operation
2.7V TO 5.5V 1F 2 VCC LTC2413 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 3 4 5 6 REF + REF - IN + IN - GND SDO CS 12 11 SCK 13 3-WIRE SPI INTERFACE FO 14 = EXTERNAL OSCILLATOR = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION
VCC
10k
1, 7, 8, 9, 10, 15, 16
BIT 30
BIT 29 SIG
BIT 28 MSB
BIT 27
BIT 26
BIT 5 LSB24
BIT 0
Hi-Z
Hi-Z
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LTC2413
APPLICATIO S I FOR ATIO
then tEOCtest is 3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. If CS remains LOW longer than tEOCtest, the first rising edge of SCK will occur and the conversion result is serially shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays HIGH and a new conversion starts. Typically, CS remains LOW during the data output state. However, the data output state may be aborted by pulling CS HIGH anytime between the first and 32nd rising edge of SCK, see Figure 10. On the rising edge of CS, the device aborts the data output state and immediately initiates a
REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF
1, 7, 8, 9, 10, 15, 16
> tEOCtest CS TEST EOC TEST EOC
BIT 0 SDO Hi-Z EOC Hi-Z
BIT 31 EOC
Hi-Z
Hi-Z
SCK (INTERNAL) SLEEP CONVERSION DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
2413 F10
Figure 10. Internal Serial Clock, Reduced Data Output Length
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new conversion. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. If CS is pulled HIGH while the converter is driving SCK LOW, the internal pull-up is not available to restore SCK to a logic HIGH state. This will cause the device to exit the internal serial clock mode on the next falling edge of CS. This can be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW. Whenever SCK is LOW, the LTC2413's internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2413's internal pull-up remains disabled. Hence, SCK remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an external 10k pull-up resistor to SCK, this pin goes HIGH once the external driver goes Hi-Z. On the next CS falling edge, the device will remain in the internal SCK timing mode.
VCC 14 = EXTERNAL OSCILLATOR = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION 2.7V TO 5.5V 1F 2 VCC LTC2413 3 4 5 6 REF + REF - IN + IN - GND SDO CS 12 11 SCK 13 3-WIRE SPI INTERFACE FO 10k BIT 30 BIT 29 SIG BIT 28 MSB Hi-Z BIT 27 BIT 26 BIT 8 TEST EOC
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LTC2413
APPLICATIO S I FOR ATIO
A similar situation may occur during the sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0), SCK will go LOW. Once CS goes HIGH (within the time period defined above as tEOCtest), the internal pull-up is activated. For a heavy capacitive load on the SCK pin, the internal pull-up may not be adequate to return SCK to a HIGH level before CS goes low again. This is not a concern under normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an external 10k pull-up resistor to the SCK pin. Internal Serial Clock, 2-Wire I/O, Continuous Conversion This timing mode uses a 2-wire, all output (SCK and SDO) interface. The conversion result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 11. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The internal serial clock mode is selected at the end of the power-on reset (POR) cycle. The POR cycle is concluded approximately 0.5ms after VCC exceeds 2.2V. An internal
REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF
1, 7, 8, 9, 10, 15, 16 CS
SDO
BIT 31 EOC
BIT 30
BIT 29 SIG
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2413 F11
Figure 11. Internal Serial Clock, CS = 0 Continuous Operation
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weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven LOW (if SCK is loaded such that the internal pull-up cannot pull the pin HIGH, the external SCK mode will be selected). During the conversion, the SCK and the serial data output pin (SDO) are HIGH (EOC = 1). Once the conversion is complete, SCK and SDO go LOW (EOC = 0) indicating the conversion has finished and the device has entered the low power sleep state. The part remains in the sleep state a minimum amount of time (1/2 the internal SCK period) then immediately begins outputting data. The data output cycle begins on the first rising edge of SCK and ends after the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK. After the 32nd rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion.
2.7V TO 5.5V 1F 2 VCC LTC2413 3 4 5 6 REF + REF - IN + IN - GND SDO CS 12 11 SCK 13 2-WIRE I/O FO 14 = EXTERNAL OSCILLATOR = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION BIT 28 MSB BIT 27 BIT 26 BIT 5 LSB24 BIT 0
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LTC2413
APPLICATIO S I FOR ATIO
Internal Serial Clock, Autostart Conversion This timing mode is identical to the internal serial clock, 2-wire I/O described above with one additional feature. Instead of grounding CS, an external timing capacitor is tied to CS. While the conversion is in progress, the CS pin is held HIGH by an internal weak pull-up. Once the conversion is complete, the device enters the low power sleep state and an internal 25nA current source begins discharging the capacitor tied to CS, see Figure 12. The time the converter spends in the sleep state is determined by the value of the external timing capacitor, see Figures 13 and 14. Once the voltage at CS falls below an internal threshold (1.4V), the device automatically begins outputting data. The data output cycle begins on the first rising edge of SCK and ends on the 32nd rising edge. Data is shifted out the SDO pin on each falling edge of SCK. The internally generated serial clock is output to the SCK pin. This signal may be
2.7V TO 5.5V 1F 2 VCC LTC2413 REFERENCE VOLTAGE 0.1V TO VCC ANALOG INPUT RANGE -0.5VREF TO 0.5VREF 3 4 5 6 REF + REF IN + IN - GND
-
1, 7, 8, 9, 10, 15, 16
VCC CS GND BIT 31 SDO Hi-Z EOC BIT 30 BIT 29 SIG Hi-Z BIT 0
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2413 F12
Figure 12. Internal Serial Clock, Autostart Operation
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used to shift the conversion result into external circuitry. After the 32nd rising edge, CS is pulled HIGH and a new conversion is immediately started. This is useful in applications requiring periodic monitoring and ultralow power. Figure 15 shows the average supply current as a function of capacitance on CS. It should be noticed that the external capacitor discharge current is kept very small in order to decrease the converter power dissipation in the sleep state. In the autostart mode, the analog voltage on the CS pin cannot be observed without disturbing the converter operation using a regular oscilloscope probe. When using this configuration, it is important to minimize the external leakage current at the CS pin by using a low leakage external capacitor and properly cleaning the PCB surface. The internal serial clock mode is selected every time the voltage on the CS pin crosses an internal threshold voltage. An internal weak pull-up at the SCK pin is active while
FO 14 = EXTERNAL OSCILLATOR = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION SCK 13 2-WIRE I/O SDO CS 12 11 CEXT
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LTC2413
APPLICATIO S I FOR ATIO
7 6 5
tSAMPLE (SEC)
4 3 2 VCC = 5V 1 0 1 10 VCC = 3V 100 1000 10000 CAPACITANCE ON CS (pF) 100000
2413 F13
Figure 13. CS Capacitance vs tSAMPLE
8 7 6
SAMPLE RATE (Hz)
5 4 3 2 1 0 0 10
VCC = 5V VCC = 3V
100 10000 100000 1000 CAPACITANCE ON CS (pF)
2413 F14
Figure 14. CS Capacitance vs Output Rate
300 250
SUPPLY CURRENT (ARMS)
VCC = 5V
200 VCC = 3V 150 100 50 0 1 10 100 1000 10000 CAPACITANCE ON CS (pF) 100000
2413 F15
Figure 15. CS Capacitance vs Supply Current
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CS is discharging; therefore, the internal serial clock timing mode is automatically selected if SCK is floating. It is important to ensure there are no external drivers pulling SCK LOW while CS is discharging. PRESERVING THE CONVERTER ACCURACY The LTC2413 is designed to reduce as much as possible the conversion result sensitivity to device decoupling, PCB layout, antialiasing circuits, line frequency perturbations and so on. Nevertheless, in order to preserve the extreme accuracy capability of this part, some simple precautions are desirable. Digital Signal Levels The LTC2413's digital interface is easy to use. Its digital inputs (FO, CS and SCK in External SCK mode of operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100s. However, some considerations are required to take advantage of the exceptional accuracy and low supply current of this converter. The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the conversion state. While a digital input signal is in the range 0.5V to (VCC - 0.5V), the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the LTC2413 power supply current may increase even if the signal in question is at a valid logic level. For micropower operation, it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VIH > (VCC - 0.4V)]. During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the LTC2413 pins may severely disturb the analog to digital conversion process. Undershoot and overshoot can occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2413. For reference, on a regular FR-4 board, signal propagation
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LTC2413
APPLICATIO S I FOR ATIO
velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance. Parallel termination near the LTC2413 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 and 56 placed near the driver or near the LTC2413 pin will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. An alternate solution is to reduce the edge rate of the control signals. It should be noted that using very slow edges will increase the converter power supply current during the transition time. The multiple ground pins used in this package configuration, as well as the differential input and reference architecture, reduce substantially the converter's sensitivity to ground currents. Particular attention must be given to the connection of the FO signal when the LTC2413 is used with an external conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the converter reference terminals may result in DC gain and INL errors. A normal mode signal of this frequency at the converter input terminals may result in a DC offset error. Such perturbations may occur due to asymmetric capacitive coupling between the FO signal trace and the converter input and/or reference connection traces. An immediate solution is to maintain maximum possible separation between the FO signal trace and the input/reference signals. When the FO signal is parallel terminated near the converter, substantial AC current is flowing in the loop formed by the FO connection trace, the termination and the ground return path. Thus, perturbation signals may be inductively coupled into the converter input and/or refer-
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ence. In this situation, the user must reduce to a minimum the loop area for the FO signal as well as the loop area for the differential input and reference connections. Driving the Input and Reference The input and reference pins of the LTC2413 converter are directly connected to a network of sampling capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transfering small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 16. For a simple approximation, the source impedance RS driving an analog input pin (IN+, IN-, REF+ or REF-) can be considered to form, together with RSW and CEQ (see Figure 16), a first order passive network with a time constant = (RS + RSW) * CEQ. The converter is able to sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant . The sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worstcase circumstances, the errors may add. When using the internal oscillator (FO = LOW), the LTC2413's front-end switched-capacitor network is clocked at 69900Hz corresponding to a 14.3s sampling period. Thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that 14.3s/14 = 1.02s. When an external oscillator of frequency fEOSC is used, the sampling period is 2/fEOSC and, for a settling error of less than 1ppm, 0.14/fEOSC. Input Current If complete settling occurs on the input, conversion results will be unaffected by the dynamic input current. An incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade the INL performance of the converter. Figure 16 shows the mathematical expressions for the average bias currents flowing through the IN + and IN - pins as a result of the sampling charge transfers when integrated over a substantial time period (longer than 64 internal clock cycles).
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LTC2413
APPLICATIO S I FOR ATIO
IREF+ VREF+ ILEAK IIN+ VIN+ ILEAK IIN - VIN - ILEAK IREF - VREF - ILEAK VCC ILEAK RSW (TYP) 20k
2413 F16
VCC ILEAK RSW (TYP) 20k
VCC ILEAK RSW (TYP) 20k CEQ 18pF (TYP) RSW (TYP) 20k
VCC ILEAK
SWITCHING FREQUENCY fSW = 69900Hz INTERNAL OSCILLATOR fSW = 0.5 * fEOSC EXTERNAL OSCILLATOR
Figure 16. LTC2413 Equivalent Analog Input Circuit
The effect of this input dynamic current can be analyzed using the test circuit of Figure 17. The CPAR capacitor includes the LTC2413 pin capacitance (5pF typical) plus the capacitance of the test fixture used to obtain the results shown in Figures 18 and 19. A careful implementation can bring the total input capacitance (CIN + CPAR) closer to 5pF thus achieving better performance than the one predicted by Figures 18 and 19. For simplicity, two distinct situations can be considered.
50 CIN = 0.01F CIN = 0.001F CIN = 100pF CIN = 0pF 30 VCC = 5V REF + = 5V REF - = GND IN + = 5V IN - = 2.5V FO = GND TA = 25C 1.E+01 1.E+02 1.E+03 RSOURCE () 1.E+04 1.E+05
2413 F18
-FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
40
20
10
0 1.E+00
Figure 18. +FS Error vs RSOURCE at IN+ or IN- (Small CIN)
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V ( )AVG = VIN + VINCMR-EQREFCM 0.5 * -V + VINCM - VREFCM = IN I(IN- ) AVG 0.5 * REQ I IN+ I REF + I REF - where: VREF = REF + - REF - REF + + REF - VREFCM = 2 VIN = IN+ - IN- IN+ - IN- VINCM = 2 REQ = 3.97M INTERNAL OSCILLATOR REQ = 0.555 * 1012 / fEOSC EXTERNAL OSCILLATOR
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(
)AVG = 1.5 * VREF0-5V*INCM + VREFCM - VREF INREQ * . REQ
V )AVG = -1.5 * VREF .- *INCM + VREFCM + VREF INREQ 0 5 REQ * V2
V2
(
(
)
RSOURCE CPAR 20pF
IN + CIN
VINCM + 0.5VIN
LTC2413
RSOURCE CPAR 20pF
IN - CIN
2413 F17
VINCM - 0.5VIN
Figure 17. An RC Network at IN + and IN -
0 VCC = 5V REF + = 5V REF - = GND IN + = GND IN - = 2.5V FO = GND TA = 25C
-10
-20
-30 CIN = 0.01F -40 CIN = 0.001F CIN = 100pF CIN = 0pF 1.E+01 1.E+02 1.E+03 RSOURCE () 1.E+04 1.E+05
2413 F19
-50 1.E+00
Figure 19. -FS Error vs RSOURCE at IN+ or IN- (Small CIN)
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LTC2413
APPLICATIO S I FOR ATIO
For relatively small values of input capacitance (CIN < 0.01F), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CIN will deteriorate the converter offset and gain performance without significant benefits of signal filtering and the user is advised to avoid them. Nevertheless, when small values of CIN are unavoidably present as parasitics of input multiplexers, wires, connectors or sensors, the LTC2413 can maintain its exceptional accuracy while operating with relative large values of source resistance as shown in Figures 18 and 19. These measured results may be slightly different from the first order approximation suggested earlier because they include the effect of the actual second order input network together with the nonlinear settling process of the input amplifiers. For small CIN values, the settling on IN+ and IN - occurs almost independently and there is little benefit in trying to match the source impedance for the two pins. Larger values of input capacitors (CIN > 0.01F) may be required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the input sampling charge and the external source resistance will see a quasi constant input differential impedance. When internal oscillator is used (FO= LOW), the typical differential input resistance is 2M which will generate a gain error of approximately 0.25ppm for each ohm of source resistance driving IN+ or IN -. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential input resistance is 0.28 * 1012/fEOSC and each ohm of source resistance driving IN+ or IN - will result in 1.78 * 10-6 * fEOSCppm gain error. The effect of the source resistance on the two input pins is additive with respect to this gain error. The typical +FS and -FS errors as a function of the sum of the source resistance seen by IN+ and IN- for large values of CIN are shown in Figures 20 and 21. In addition to this gain error, an offset error term may also appear. The offset error is proportional with the mismatch between the source impedance driving the two input pins IN+ and IN- and with the difference between the input and reference common mode voltages. While the input drive circuit nonzero source impedance combined with the
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converter average input current will not degrade the INL performance, indirect distortion may result from the modulation of the offset error by the common mode component of the input signal. Thus, when using large CIN capacitor values, it is advisable to carefully match the source impedance seen by the IN+ and IN- pins. When internal oscillator is used (FO = LOW), every 1 mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 0.25ppm. When FO is driven by an external oscillator with a frequency fEOSC, every 1 mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input signal of 1.78 * 10-6 * fEOSCppm. Figure 22 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN- pins when large CIN values are used. If possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. This configuration eliminates the offset error caused by mismatched source impedances. The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/C) are used for the external source impedance seen by IN+ and IN-, the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range). Even for the most stringent applications a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (10nA max), results in a small offset shift. A 100 source resistance will create a 0.1V typical and 1V maximum offset voltage.
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LTC2413
APPLICATIO S I FOR ATIO
300 VCC = 5V REF + = 5V REF - = GND IN + = 3.75V IN - = 1.25V FO = GND TA = 25C CIN = 1F, 10F
+FS ERROR (ppm OF VREF)
240
180
120
CIN = 0.1F
60
CIN = 0.01F
0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE ()
2413 F19
Figure 20. +FS Error vs RSOURCE
0
at IN+
or IN- (Large C
CIN = 0.01F
-FS ERROR (ppm OF VREF)
-60
-120 CIN = 0.1F -180 VCC = 5V REF + = 5V REF - = GND IN + = 1.25V IN - = 3.75V FO = GND TA = 25C
-240
CIN = 1F, 10F
-300 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE ()
2413 F21
Figure 21. -FS Error vs RSOURCE
120 100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 0 0.5 1 1.5 G B C D E F A
at IN+
or IN-
(Large CIN)
OFFSET ERROR (ppm OF VREF)
VCC = 5V REF + = 5V REF - = GND IN + = IN - = VINCM
FO = GND TA = 25C RSOURCEIN - = 500 CIN = 10F 2 2.5 3 VINCM (V) 3.5 4 4.5 5
A: RIN = +400 B: RIN = +200 C: RIN = +100 D: RIN = 0
E: RIN = -100 F: RIN = -200 G: RIN = -400
2413 F22
Figure 22. Offset Error vs Common Mode Voltage (VINCM = IN+ = IN-) and Input Source Resistance Imbalance (RIN = RSOURCEIN+ - RSOURCEIN-) for Large CIN Values (CIN 1F)
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Reference Current In a similar fashion, the LTC2413 samples the differential reference pins REF+ and REF- transfering small amount of charge to and from the external driving circuits, thus produces a dynamic reference current. This current does not change the converter offset but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations. For relatively small values of the external reference capacitors (CREF < 0.01F), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for CREF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them. Larger values of reference capacitors (CREF > 0.01F) may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. When internal oscillator is used (FO = LOW), the typical differential input resistance is 1.43M which will generate a gain error of approximately 0.35ppm for each ohm of source resistance driving REF+ or REF-. When FO is driven by an external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference resistance is 0.20 * 1012/fEOSC and each ohm of source resistance drving REF + or REF - will result in 2.47 * 10-6 * fEOSCppm gain error. The effect of the source resistance on the two reference pins is additive with respect to this gain error. The typical +FS and -FS errors for various combinations of source resistance seen by the REF+ and REF- pins and external capacitance CREF connected to these pins are shown in Figures 23, 24, 25 and 26. In addition to this gain error, the converter INL performance is degraded by the reference source impedance. When internal oscillator is used(FO = LOW), every 100 of source impedance driving REF+ or REF- translates into about 1.2ppm additional INL error. When FO is driven by an external oscillator with a frequency fEOSC, every 100 of source resistance driving REF+ or REF- translates into about 8.73 * 10-6 * fEOSCppm additional INL error.
IN)
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LTC2413
APPLICATIO S I FOR ATIO
Figure 27 shows the typical INL error due to the source resistance driving the REF+ or REF- pins when large CREF values are used. The effect of the source resistance on the two reference pins is additive with respect to this INL error. In general, matching of source impedance for the REF+ and REF- pins does not help the gain or the INL error. The user is thus advised to minimize the combined source impedance driving the REF+ and REF- pins rather than to try to match it. The magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typical better than
0 VCC = 5V REF + = 5V REF - = GND IN + = 5V IN - = 2.5V FO = GND TA = 25C
-FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
-10
-20
-30 CREF = 0.01F -40 CREF = 0.001F CREF = 100pF CREF = 0pF 1.E+01 1.E+02 1.E+03 RSOURCE () 1.E+04 1.E+05
2413 F23
-50 1.E+00
Figure 23. +FS Error vs RSOURCE at REF+ or REF- (Small CREF)
0
CREF = 0.01F
-FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
-90
-180 VCC = 5V REF + = 5V REF - = GND IN + = 3.75V IN - = 1.25V FO = GND TA = 25C
CREF = 0.1F
-270
-360
CREF = 1F, 10F
-450 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE ()
2413 F25
Figure 25. +FS Error vs RSOURCE at REF+ or REF- (Large CREF)
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0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/C) are used for the external source impedance seen by REF+ and REF-, the expected drift of the dynamic current gain error will be insignificant (about 1% of its value over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (10nA max), results in a small gain error. A 100 source resistance will create a 0.05V typical and 0.5V maximum full-scale error.
50 CREF = 0.01F CREF = 0.001F 40 CREF = 100pF CREF = 0pF 30 VCC = 5V REF + = 5V REF - = GND IN + = GND IN - = 2.5V FO = GND TA = 25C 1.E+01 1.E+02 1.E+03 RSOURCE () 1.E+04 1.E+05
2413 F24
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10
0 1.E+00
Figure 24. -FS Error vs RSOURCE at REF+ or REF- (Small CREF)
450 VCC = 5V REF + = 5V REF - = GND IN + = 1.25V IN - = 3.75V FO = GND TA = 25C CREF = 1F, 10F
360
270
180
CREF = 0.1F
90
CREF = 0.01F
0 0 100 200 300 400 500 600 700 800 900 1000 RSOURCE ()
2413 F26
Figure 26. -FS Error vs RSOURCE at REF+ or REF- (Large CREF)
LTC2413
APPLICATIO S I FOR ATIO
15 12 9 INL (ppm OF VREF) 6 3 0 -3 -6 -9 -12 -15 -0.5 -0.4-0.3-0.2-0.1 0 0.1 0.2 0.3 0.4 0.5 VINDIF/VREFDIF VCC = 5V FO = GND REF+ = 5V CREF = 10F TA = 25C REF- = GND 2413 F27 VINCM = 0.5 * (IN + + IN -) = 2.5V RSOURCE = 100 RSOURCE = 500 RSOURCE = 1000
Figure 27. INL vs Differential Input Voltage (VIN = IN+ - IN-) and Reference Source Resistance (RSOURCE at REF+ and REF- for Large CREF Values (CREF 1F)
Output Data Rate When using its internal oscillator, the LTC2413 can produce up to 6.8 readings per second. The actual output data rate will depend upon the length of the sleep and data output phases which are controlled by the user and which can be made insignificantly short. When operated with an external conversion clock (FO connected to an external oscillator), the LTC2413 output data rate can be increased as desired. The duration of the conversion phase is 20510/ fEOSC. If fEOSC = 139800Hz, the converter behaves as if the internal oscillator is used with simultaneous 50Hz/60Hz rejection. There is no significant difference in the LTC2413 performance between these two operation modes. An increase in fEOSC over the nominal 139800Hz will translate into a proportional increase in the maximum output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must be carefully considered.
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First, a change in fEOSC will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power-line frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2413's exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. The user should avoid single-ended input filters and should maintain a very high degree of matching and symmetry in the circuits driving the IN+ and IN- pins. Second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. If large external input and/or reference capacitors (CIN, CREF) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/ or reference capacitors (CIN, CREF) are used, the effect of the external source resistance upon the LTC2413 typical performance can be inferred from Figures 18, 19, 23 and 24 in which the horizontal axis is scaled by 139800/fEOSC.
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LTC2413
APPLICATIO S I FOR ATIO
Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3x increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity. Typical measured performance curves for output data rates up to 100 readings per second are shown in Fig-
500 450 OFFSET ERROR (ppm OF VREF) 400 350 300 250 200 150 100 50 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2413 F28
Figure 28. Offset Error vs Output Data Rate and Temperature
7000 6000
+FS ERROR (ppm OF VREF)
5000 4000 3000
-FS ERROR (ppm OF VREF)
VCC = 5V REF + = 5V REF - = GND IN + = 3.75V IN - = 1.25V FO = EXTERNAL OSCILLATOR
TA = 85C 2000 TA = 25C 1000 0
0
10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2413 F29
Figure 29. +FS Error vs Output Data Rate and Temperature
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ures 28 through 35, inclusive. In order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial.
VCC = 5V REF + = 5V REF - = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR TA = 85C TA = 25C 0 -1000 TA = 85C -2000 -3000 -4000 -5000 -6000 -7000 VCC = 5V REF + = 5V REF - = GND IN + = 1.25V IN - = 3.75V FO = EXTERNAL OSCILLATOR 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2413 F30
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TA = 25C
Figure 30. -FS Error vs Output Data Rate and Temperature
LTC2413
APPLICATIO S I FOR ATIO
24 23 22 RESOLUTION (BITS) 21 20 19 18 17 16 15 14 13 12 0 TA = 85C VCC = 5V REF + = 5V REF - = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR RESOLUTION = LOG2(VREF/NOISERMS) 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2413 F31
TA = 25C RESOLUTION (BITS) 18 TA = 85C 16 14 12 10 8 VCC = 5V REF + = 5V REF - = GND VINCM = 2.5V -2.5V < VIN < 2.5V FO = EXTERNAL OSCILLATOR 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2413 F32
Figure 31. Resolution (NoiseRMS 1LSB) vs Output Data Rate and Temperature
250 225 OFFSET ERROR (ppm OF VREF) 200 175 150 125 100 75 50 25 0 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2413 F33
RESOLUTION (BITS)
VCC = 5V REF + = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR TA = 25C
VREF = 5V VREF = 2.5V
Figure 33. Offset Error vs Output Data Rate and Reference Voltage
22 20 RESOLUTION (BITS) 18 16 VREF = 2.5V 14 12 10 8 TA = 25C VCC = 5V REF - = GND VINCM = 0.5 * REF + -0.5V * VREF < VIN < 0.5 * VREF FO = EXTERNAL OSCILLATOR 0 VREF = 5V
Figure 35. Resolution (INLMAX 1LSB) vs Output Data Rate and Reference Voltage
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22 20 RESOLUTION = LOG2(VREF/INLMAX) TA = 25C
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Figure 32. Resolution (INLRMS 1LSB) vs Output Data Rate and Temperature
24 23 22 21 20 19 18 17 16 15 14 13 12 0 VCC = 5V REF - = GND VINCM = 2.5V VIN = 0V FO = EXTERNAL OSCILLATOR TA = 25C RESOLUTION = LOG2(VREF/NOISERMS) 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2413 F34
VREF = 5V VREF = 2.5V
Figure 34. Resolution (NoiseRMS 1LSB) vs Output Data Rate and Reference Voltage
RESOLUTION = LOG2(VREF/INLMAX)
10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC)
2413 F35
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LTC2413
APPLICATIO S I FOR ATIO
Input Bandwidth The combined effect of the internal sinc4 digital filter and of the analog and digital autocalibration circuits determines the LTC2413 input bandwidth. When the internal oscillator is used (FO = LOW), the 3dB input bandwidth is 3.3Hz. If an external conversion clock generator of frequency fEOSC is connected to the FO pin, the 3dB input bandwidth is 0.236 * 10-6 * fEOSC. Due to the complex filtering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a first order filter with the pole located at the 3dB frequency. When the internal oscillator is used, the shape of the LTC2413 input bandwidth is shown in Figure 36. When an external oscillator of frequency fEOSC is used, the shape of the LTC2413 input bandwidth can be derived from Figure 36, in which the horizontal axis is scaled by fEOSC/139800. The conversion noise (800nVRMS typical for VREF = 5V) can be modeled as a white noise source connected to a noise free converter. The noise spectral density is 63nV/Hz for an infinite bandwidth source and 77nV/Hz for a single 0.5MHz pole source. From these numbers, it is clear that particular attention must be given to the design of external amplification circuits. Such circuits face the simultaneous requirements of very low bandwidth (just a few Hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500kHz) necessary to drive the input switched-capacitor network. A possible solution is a
0.0 -0.5
INPUT SIGNAL ATTENUATION (dB)
INPUT REFERRED NOISE EQUIVALENT BANDWIDTH (Hz)
-1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2413 F36
Figure 36. Input Signal Bandwidth Using the Internal Oscillator
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high gain, low bandwidth amplifier stage followed by a high bandwidth unity-gain buffer. When external amplifiers are driving the LTC2413, the ADC input referred system noise calculation can be simplified by Figure 37. The noise of an amplifier driving the LTC2413 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated by the bandwidth of a single pole lowpass filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 37, using fi as the x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal calibration and filtering. The noise of the driving amplifier referred to the converter input and including all these effects can be calculated as N = ni * freqi. The total system noise (referred to the LTC2413 input) can now be obtained by summing as square root of sum of squares the three ADC input referred noise sources: the LTC2413 internal noise (800nV), the noise of the IN + driving amplifier and the noise of the IN - driving amplifier. If the FO pin is driven by an external oscillator of frequency fEOSC, Figure 37 can still be used for noise calculation if the x-axis is scaled by fEOSC/139800. For large values of the ratio fEOSC/139800, the Figure 37 plot accuracy begins to decrease, but in the same time the LTC2413 noise floor rises and the noise contribution of the driving amplifiers lose significance.
1000 100 10 FO = LOW 1 0.1 0.1 1 10 100 1k 10k 100k 1M INPUT NOISE SOURCE SINGLE POLE EQUIVALENT BANDWIDTH (Hz) 2413 F37
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Figure 37. Input Referred Noise Equivalent Bandwidth of an Input Connected White Noise Source
LTC2413
APPLICATIO S I FOR ATIO
Normal Mode Rejection and Antialiasing One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with a large oversampling ratio, the LTC2413 significantly simplifies antialiasing filter requirements. The sinc4 digital filter provides greater than 120dB normal mode rejection at all frequencies except DC and integer multiples of the modulator sampling frequency (fS). The LTC2413's autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal filtering both in the analog and digital domain. Independent of the operating mode, fS = 256 * fN = 2048 * fOUTMAX where fN in the notch frequency and fOUTMAX is
0
INPUT NORMAL MODE REJECTION (dB)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2413 F38
Figure 38. Input Normal Mode Rejection
0
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN INPUT SIGNAL FREQUENCY (Hz) 8fN
2413 F39
Figure 39. Input Normal Mode Rejection
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the maximum output data rate. In the internal oscillator mode, fS = 13980Hz. In the external oscillator mode, fS = fEOSC/10. The combined normal mode rejection performance is shown in Figure 38. The regions of low rejection occurring at integer multiples of fS have a very narrow bandwidth. Magnified details of the normal mode rejection curves are shown in Figure 39 (rejection near DC) and Figure 40 (rejection at fS = 256fN) where fN represents the notch frequency. These curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the fN value.
FO = LOW OR FO = EXTERNAL OSCILLATOR, fEOSC = 10 * fS 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz)
2413 F40
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Figure 40. Input Normal Mode Rejection
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LTC2413
APPLICATIO S I FOR ATIO
The user can expect to achieve in practice this level of performance using the internal oscillator, as it is demonstrated by Figure 41. Typical measured values of the normal mode rejection of the LTC2413 operating with the internal oscillator are shown in Figure 41 superimposed over the theoretical calculated curve. As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front of the LTC2413. If passive RC components are placed in front of the LTC2413, the input dynamic current should be considered (see Input Current section). In cases where large effective RC time constants are used, an external buffer amplifier may be required to minimize the effects of dynamic input current.
0
NORMAL MODE REJECTION (dB)
-20 -40 - 60 -80 -100 -120
0
20
40
Figure 41. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% of Full Scale
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Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary architecture used for the LTC2413 third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. In many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and LTC2413 is eminently suited for such tasks. When the perturbation is differential, the specification of interest is the normal mode rejection for large input signal levels. With a reference voltage VREF = 5V, the LTC2413 has a full-scale differential input
MEASURED DATA CALCULATED DATA VCC = 5V REF + = 5V REF - = GND VINCM = 2.5V VIN(P-P) = 5V TA = 25C 60 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 200 220
2413 F41
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LTC2413
APPLICATIO S I FOR ATIO
range of 5V peak-to-peak. Figure 42 shows measurement results for the LTC2413 normal mode rejection ratio with a 7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection ratio results obtained with a 5V peak-to-peak (full scale) input signal. It is clear that the LTC2413 rejection performance is maintained with no compromises in this extreme situation. When operating with large input signal levels, the user must observe that such signals do not violate the device's absolute maximum ratings. BRIDGE APPLICATIONS Typical strain gauge based bridges deliver only 2mV/Volt of excitation. As the maximum reference voltage of the LTC2413 is 5V, remote sensing of applied excitation without additional circuitry requires that excitation be
0
NORMAL MODE REJECTION (dB)
-20 -40 - 60 -80 -100 -120
0
20
40
60
Figure 42. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% of Full Scale
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limited to 5V. This gives only 10mV full scale, which can be resolved to 1 part in 10000 without averaging. For many solid state sensors, this is still better than the sensor. For example, averaging 64 samples however reduces the noise level by a factor of eight, bringing the resolving power to 1 part in 80000, comparable to better weighing systems. Hysteresis and creep effects in the load cells are typically much greater than this. Most applications that require strain measurements to this level of accuracy are measuring slowly changing phenomena, hence the time required to average a large number of readings is usually not an issue. For those systems that require accurate measurement of a small incremental change on a significant tare weight, the lack of history effects in the LTC2400 family is of great benefit.
VIN(P-P) = 5V VIN(P-P) = 7.5V (150% OF FULL SCALE) VCC = 5V REF + = 5V REF - = GND VINCM = 2.5V TA = 25C 80 100 120 140 INPUT FREQUENCY (Hz) 160 180 200 220
2413 F42
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LTC2413
APPLICATIO S I FOR ATIO
For those applications that cannot be fulfilled by the LTC2413 alone, compensating for error in external amplification can be done effectively due to the "no latency" feature of the LTC2413. No latency operation allows samples of the amplifier offset and gain to be interleaved with weighing measurements. The use of correlated double sampling allows suppression of 1/f noise, offset and thermocouple effects within the bridge. Correlated double sampling involves alternating the polarity of excitation and dealing with the reversal of input polarity mathematically. Alternatively, bridge excitation can be increased to as much as 10V, if one of several precision attenuation techniques is used to produce a precision divide operation on the reference signal. Another option is the use of a reference within the 5V input range of the LTC2413 and developing excitation via fixed gain, or LTC1043 based voltage multiplication, along with remote feedback in the excitation amplifiers, as shown in Figures 48 and 50. Figure 43 shows an example of a simple bridge connection. Note that it is suitable for any bridge application where measurement speed is not of the utmost importance. For many applications where large vessels are weighed, the average weight over an extended period of time is of concern and short term weight is not readily determined due to movement of contents, or mechanical resonance. Often, large weighing applications involve load
R1 3 350 BRIDGE 4 5 REF + REF - IN +
R2
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
Figure 43. Simple Bridge Connection
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cells located at each load bearing point, the output of which can be summed passively prior to the signal processing circuitry, actively with amplification prior to the ADC, or can be digitized via multiple ADC channels and summed mathematically. The mathematical summation of the output of multiple LTC2413's provides the benefit of a root square reduction in noise. The low power consumption of the LTC2413 makes it attractive for multidrop communication schemes where the ADC is located within the load-cell housing. A direct connection to a load cell is perhaps best incorporated into the load-cell body, as minimizing the distance to the sensor largely eliminates the need for protection devices, RFI suppression and wiring. The LTC2413 exhibits extremely low temperature dependent drift. As a result, exposure to external ambient temperature ranges does not compromise performance. The incorporation of any amplification considerably complicates thermal stability, as input offset voltages and currents, temperature coefficient of gain settling resistors all become factors. The circuit in Figure 44 shows an example of a simple amplification scheme. This example produces a differential output with a common mode voltage of 2.5V, as determined by the bridge. The use of a true three amplifier instrumentation amplifier is not necessary, as the LTC2413
+
2 VREF SDO SCK CS 12 13 11 LT1019 LTC2413 6 IN - GND FO 14 1, 7, 8, 9, 10, 15, 16
2413 F43
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LTC2413
APPLICATIO S I FOR ATIO
has common mode rejection far beyond that of most amplifiers. The LTC1051 is a dual autozero amplifier that can be used to produce a gain of 15 before its input referred noise dominates the LTC2413 noise. This example shows a gain of 34, that is determined by a feedback network built using a resistor array containing 8 individual resistors. The resistors are organized to optimize temperature tracking in the presence of thermal gradients. The second LTC1051 buffers the low noise input stage from the transient load steps produced during conversion. The gain stability and accuracy of this approach is very good, due to a statistical improvement in resistor matching due to individual error contribution being reduced. A gain of 34 may seem low, when compared to common practice in earlier generations of load-cell interfaces, however the accuracy of the LTC2413 changes the rationale. Achieving high gain accuracy and linearity at higher gains may prove difficult, while providing little benefit in terms of noise reduction. At a gain of 100, the gain error that could result from typical open-loop gain of 160dB is -1ppm, however, worst-case is at the minimum gain of 116dB, giving a gain error of -158ppm. Worst-case gain error at a gain of 34, is -54ppm. The use of the LTC1051A reduces the worstcase gain error to -33ppm. The advantage of gain higher than 34, then becomes dubious, as the input referred noise sees little improvement1 and gain accuracy is potentially compromised. Note that this 4-amplifier topology has advantages over the typical integrated 3-amplifier instrumentation amplifier in that it does not have the high noise level common in the output stage that usually dominates when an instrumentation amplifier is used at low gain. If this amplifier is used at a gain of 10, the gain error is only 10ppm and input referred noise is reduced to 0.1VRMS. The buffer stages can also be configured to provide gain of up to 50 with high gain stability and linearity.
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Figure 45 shows an example of a single amplifier used to produce single-ended gain. This topology is best used in applications where the gain setting resistor can be made to match the temperature coefficient of the strain gauges. If the bridge is composed of precision resistors, with only one or two variable elements, the reference arm of the bridge can be made to act in conjunction with the feedback resistor to determine the gain. If the feedback resistor is incorporated into the design of the load cell, using resistors which match the temperature coefficient of the loadcell elements, good results can be achieved without the need for resistors with a high degree of absolute accuracy. The common mode voltage in this case, is again a function of the bridge output. Differential gain as used with a 350 bridge is AV = (R1+ R2)/(R1+175). Common mode gain is half the differential gain. The maximum differential signal that can be used is 1/4 VREF, as opposed to 1/2 VREF in the 2-amplifier topology above. Remote Half Bridge Interface As opposed to full bridge applications, typical half bridge applications must contend with nonlinearity in the bridge output, as signal swing is often much greater. Applications include RTD's, thermistors and other resistive elements that undergo significant changes over their span. For single variable element bridges, the nonlinearity of the half bridge output can be eliminated completely; if the reference arm of the bridge is used as the reference to the ADC, as shown in Figure 46. The LTC2413 can accept inputs up to 1/2 VREF. Hence, the reference resistor R1 must be at least 2x the highest value of the variable resistor. In the case of 100 platinum RTD's, this would suggest a value of 800 for R1. Such a low value for R1 is not advisable due to self-heating effects. A value of 25.5k is shown for R1, reducing self-heating effects to acceptable levels for most sensors.
1Input referred noise for A = 34 for approximately 0.05V V RMS, whereas at a gain of 50, it would be 0.048VRMS.
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LTC2413
APPLICATIO S I FOR ATIO
The basic circuit shown in Figure 46 shows connections for a full 4-wire connection to the sensor, which may be located remotely. The differential input connections will reject induced or coupled 60Hz interference, however, the reference inputs do not have the same rejection. If 60Hz or other noise is present on the reference input, a low pass filter is recommended as shown in Figure 47. Note that you cannot place a large capacitor directly at the junction of R1 and R2, as it will store charge from the sampling process. A better approach is to produce a low pass filter decoupled from the input lines with a high value resistor (R3). The use of a third resistor in the half bridge, between the variable and fixed elements gives essentially the same result as the two resistor version, but has a few benefits. If, for example, a 25k reference resistor is used to set the excitation current with a 100 RTD, the negative reference input is sampling the same external node as the positive input, but may result in errors if used with a long cable. For short cable applications, the errors may be acceptably low. If instead the single 25k resistor is replaced with a 10k 5% and a 10k 0.1% reference resistor, the noise level introduced at the reference, at least at
5V 3
+ -
8 U1A 1 2 0.1F 5V 8 U2A 1 3 4 4 5 REF + REF - IN + LTC2413 U2B 5 7 6 IN - GND FO 14 VCC SDO SCK CS 2 12 13 11 0.1F
2 350 BRIDGE
4 15 1 RN1 16 6 11 2 6 7 10 3 8 9 13 14 4 5 12
-
U1B 7
5
+
RN1 = 5k x 8 RESISTOR ARRAY U1A, U1B, U2A, U2B = 1/2 LTC1051
Figure 44. Using Autozero Amplifiers to Reduce Input Referred Noise
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higher frequencies, will be reduced. A filter can be introduced into the network, in the form of one or more capacitors, or ferrite beads, as long as the sampling pulses are not translated into an error. The reference voltage is also reduced, but this is not undesirable, as it will decrease the value of the LSB, although, not the input referred noise level. The circuit shown in Figure 47 shows a more rigorous example of Figure 46, with increased noise suppression and more protection for remote applications. Figure 48 shows an example of gain in the excitation circuit and remote feedback from the bridge. The LTC1043's provide voltage multiplication, providing 10V from a 5V reference with only 1ppm error. The amplifiers are used at unity-gain and, hence, introduce a very little error due to gain error or due to offset voltages. A 1V/C offset voltage drift translates into 0.05ppm/C gain error. Simpler alternatives, with the amplifiers providing gain using resistor arrays for feedback, can produce results that are similar to bridge sensing schemes via attenuators. Note that the amplifiers must have high open-loop gain or gain error will
5VREF 0.1F
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3
6
- +
1, 7, 8, 9, 10, 15, 16
2413 F44
LTC2413
APPLICATIO S I FOR ATIO
be a source of error. The fact that input offset voltage has relatively little effect on overall error may lead one to use low performance amplifiers for this application. Note that the gain of a device such as an LF156, (25V/mV over temperature) will produce a worst-case error of -180ppm at a noise gain of 3, such as would be encountered in an inverting gain of 2, to produce -10V from a 5V reference. The error associated with the 10V excitation would be -80ppm. Hence, overall reference error could be as high as 130ppm, the average of the two. Figure 50 shows a similar scheme to provide excitation using resistor arrays to produce precise gain. The circuit is configured to provide 10V and -5V excitation to the bridge, producing a common mode voltage at the input to the LTC2413 of 2.5V, maximizing the AC input range for applications where induced 60Hz could reach amplitudes up to 2VRMS.
350 BRIDGE 3
2
+
1F R1 4.99k
AV = 9.95 =
(
R1 + R2 R1 + 175
Figure 45. Bridge Amplification Using a Single Amplifier
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The circuits in Figures 48 and 50 could be used where multiple bridge circuits are involved and bridge output can be multiplexed onto a single LTC2413, via an inexpensive multiplexer such as the 74HC4052. Figure 49 shows the use of an LTC2413 with a differential multiplexer. This is an inexpensive multiplexer that will contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as a protection mechanism from overvoltage. Although the bridge output may be within the input range of the A/D and multiplexer in normal operation, some thought should be given to fault conditions that could result in full excitation voltage at the inputs to the multiplexer or ADC. The use of amplification prior to the multiplexer will largely eliminate errors associated with channel leakage developing error voltages in the source impedance.
+
10F 5V 0.1V 3 6 175 4 REF + REF - IN + LTC2413 20k 6 IN - GND 1, 7, 8, 9, 10, 15, 16 2 VCC 0.1F 5V
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+ -
7
LTC1050S8 4 R2 46.4k
+
1F 20k 5
)
2413 F45
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LTC2413
APPLICATIO S I FOR ATIO U
VS 2.7V TO 5.5V 2 R1 25.5k 0.1% 3 4 REF + REF - LTC2413 5 PLATINUM 100 RTD IN + VCC 6 IN - GND 1, 7, 8, 9, 10, 15, 16
2413 F46
PLATINUM 100 RTD
Figure 47. Remote Half Bridge Sensing with Noise Suppression on Reference
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Figure 46. Remote Half Bridge Interface
5V
R2 10k 0.1% R1 10k, 5%
5V
2 3 560 4 REF + REF - LTC2413 10k 10k 5 6 IN + IN - GND 1, 7, 8, 9, 10, 15, 16
2413 F47
R3 10k 5%
+
1F LTC1050
VCC
-
LTC2413
APPLICATIO S I FOR ATIO U
15V U1 4 LTC1043 10V 1F 200 8 * 2 11 47F 7 5V
15V
Q1 2N3904
20
6
LTC1150 4
33 1k 350 BRIDGE 0.1F
33
Q2 2N3906 6 20 -15V
LTC1150 4 -15V 0.1F
1k
Figure 48. LTC1043 Provides Precise 4X Reference for Excitation Voltages
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15V
+ -
3
+
LT1236-5
10V
+
0.1F
-15V
12 14 17 0.1F 2 VCC LTC2413 3 4 5 6 REF + REF - IN + IN - GND 6 * 2 2 1, 7, 8, 9, 10, 15, 16 5V 13 10F
+
15V
U2 LTC1043
+ -
3
5
3 15 18 *FLYING CAPACITORS ARE 1F FILM (MKP OR EQUIVALENT) SEE LTC1043 DATA SHEET FOR DETAILS ON UNUSED HALF OF U1
U2 LTC1043 8
5V 4 7 *
1F FILM 200 -10V
11
12 14 17 -10V
2413 F48
13
41
LTC2413
APPLICATIO S I FOR ATIO U
5V 16 12 14 15 11 1 5 TO OTHER DEVICES 2 4 8 9 10 6 13 3 5 6 IN + IN - GND 1, 7, 8, 9, 10, 15, 16 A0 A1
2413 F49
Figure 49. Use a Differential Multiplexer to Expand Channel Capability
42
W
5V
U
U
+
47F 3 4 REF + REF -
2 VCC
74HC4052
LTC2413
LTC2413
PACKAGE DESCRIPTIO U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0.229 - 0.244 (5.817 - 6.198) 0.150 - 0.157** (3.810 - 3.988) 1 0.015 0.004 x 45 (0.38 0.10) 0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727) 23 4 56 7 8 0.004 - 0.0098 (0.102 - 0.249) 0.008 - 0.012 (0.203 - 0.305) 0.0250 (0.635) BSC
GN16 (SSOP) 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
43
LTC2413
TYPICAL APPLICATIO U
15V 20
+
1 C1 0.1F 1/2 LT1112
3
5V
Q1 2N3904 22
+
2
LT1236-5 C3 47F C1 0.1F
-
RN1 10k 10V 1 2 5V 3 4 RN1 10k 3 4 5 -5V 8 RN1 10k 5 6 7 RN1 10k 6 REF + REF - IN + IN - GND 1, 7, 8, 9, 10, 15, 16 2 VCC LTC2413
350 BRIDGE TWO ELEMENTS VARYING
33 x2 Q2, Q3 2N3906 x2 20 7
C2 0.1F
15V RN1 IS CADDOCK T914 10K-010-02 8
- +
6
1/2 LT1112 4
5
-15V
-15V
2413 F50
Figure 50. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
RELATED PARTS
PART NUMBER LT1019 LT1025 LTC1043 LTC1050 LT1236A-5 LT1460 LTC2400 LTC2401/LTC2402 LTC2404/LTC2408 LTC2410 LTC2411 LTC2415 LTC2420 LTC2424/LTC2428 DESCRIPTION Precision Bandgap Reference, 2.5V, 5V Micropower Thermocouple Cold Junction Compensator Dual Precision Instrumentation Switched Capacitor Building Block Precision Chopper Stabilized Op Amp Precision Bandgap Reference, 5V Micropower Series Reference 24-Bit, No Latency ADC in SO-8 1-/2-Channel, 24-Bit, No Latency ADC in MSOP 4-/8-Channel, 24-Bit, No Latency ADC 24-Bit, Fully Differential, No Latency ADC in SSOP-16 24-Bit, Fully Differential, No Latency ADC in MS10 24-Bit, Fully Differential, ADC 20-Bit, No Latency ADC in SO-8 4-/8-Channel, 20-Bit, No Latency ADC COMMENTS 3ppm/C Drift, 0.05% Max Initial Accuracy 80A Supply Current, 0.5C Initial Accuracy Precise Charge, Balanced Switching, Low Power No External Components 5V Offset, 1.6VP-P Noise 0.05% Max Initial Accuracy, 5ppm/C Drift 0.075% Max, 10ppm/C Max Drift 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200A 0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200A 0.29ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200A 15Hz Output Rate at 60Hz Rejection, Pin Compatible with LTC2410 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408
2413f LT/TP 0501 4K * PRINTED IN USA
44
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
(c) LINEAR TECHNOLOGY CORPORATION 2000

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